AS5510-DWLT【PDF 11/19 页】IC ENCODER MAGNETIC LIN 6-WLCSP

收藏本站

您好，
买卖IC网欢迎您。
请登录
免费注册

买卖IC网

Sheet目录60

7页 8页 9页 10页 [11页]12页 13页 14页 15页

www.ams.com/AS5510

Revision 0.1

10 - 18

AS5510

Datasheet - Detailed Description

Figure 6. Data Read (Write Pointer, Then Read) - Slave Receive and Transmit

Depending upon the state of the R/W bit, two types of data transfer are possible:

Data transfer from a master transmitter to a slave receiver. The first byte transmitted by the master is the slave address, followed by

R/W = 0. Next follows a number of data bytes. The slave returns an acknowledge bit after each received byte. If the slave does not understand

the command or data it sends a not acknowledge. Data is transferred with the most significant bit (MSB) first.

Data transfer from a slave transmitter to a master receiver. The master transmits the first byte (the slave address). The slave then

returns an acknowledge bit, followed by the slave transmitting a number of data bytes. The master returns an acknowledge bit after all received

bytes other than the last byte. At the end of the last received byte, a not acknowledge is returned. The master device generates all of the serial

clock pulses and the START and STOP conditions. A transfer is ended with a STOP condition or with a repeated START condition. Since a

repeated START condition is also the beginning of the next serial transfer, the bus is not released. Data is transferred with the most significant bit

(MSB) first.

The AS5510 can operate in the following two modes:

Slave Receiver Mode (Write Mode). Serial data and clock are received through SDA and SCL. Each byte is followed by an acknowledge

bit (or by a not acknowledge depending on the address-pointer pointing to a valid position). START and STOP conditions are recognized as the

beginning and end of a serial transfer. Address recognition is performed by hardware after reception of the slave address and direction bit (see

Figure 7). The slave address byte is the first byte received after the START condition. The slave address byte contains the 7-bit AS5510 address.

The 7-bit slave address is followed by the direction bit (R/W), which, for a write, is 0. After receiving and decoding the slave address byte the

device outputs an acknowledge on the SDA. After the AS5510 acknowledges the slave address + write bit, the master transmits a register

address to the AS5510. This sets the address pointer on the AS5510. If the address is a valid readable address the AS5510 answers by sending

an acknowledge. If the address-pointer points to an invalid position a not acknowledge is sent. The master may then transmit zero or more

bytes of data. In case of the address pointer pointing to an invalid address the received data are not stored. The address pointer will increment

after each byte transferred independent from the address being valid. If the address-pointer reaches a valid position again, the AS5510 answers

with an acknowledge and stores the data. The master generates a STOP condition to terminate the data write.

...

Start

Condition

Stop Condition or

Repeated Start Condition

MSB

R/W ACK

LSB

ACK

Slave Address

Repeated if more Bytes are transferred

发布紧急采购，3分钟左右您将得到回复。

采购需求

(若只采购一条型号，填写一行即可)

*型号	*数量	厂商	批号	封装

添加更多采购

采购需求

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

我的联系方式